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cy7c4205/cy7c4215 cy7c4225/cy7c4245 256/512/1k/4k x 18 synchronous fifos cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-45652 rev. *b revised may 25, 2011 features high speed, low power, first-in first-out (fifo) memories 256 x 18 (cy7c4205) 512 x 18 (cy7c4215) 1k x 18 (cy7c4225) 4k x 18 (cy7c4245) high speed 100 mhz ope ration (10 ns read/write cycle time) low power (i cc = 45 ma) fully asynchronous and simultaneous read and write operation empty, full, half full, and prog rammable almost empty/almost full status flags transistor-transistor logic (ttl) compatible retransmit function output enable (oe ) pin independent read and write enable pins center power and ground for reduced noise supports free running 50% duty cycle clock inputs width expansion capability depth expansion capability available in 64 pin 14 x 14 thin quad flat package (tqfp) and 64 pin 10 x 10 tqfp functional description the cy7c42x5 are high speed, low power, first-in first-out (fifo) memories with clocked read and write interfaces. all are 18 bits wide and are pin/functionally compatible to idt722x5. the cy7c42x5 can be cascaded to increase fifo depth. programmable features include almost full/almost empty flags. these fifos provide solutions for a wide variety of data buffering needs, including high speed data acquisition, multipro- cessor interfaces, and communications buffering. these fifos have 18-bit input and output ports that are controlled by separate clock and enable signals. the input port is controlled by a free-running clock (wclk) and a write enable pin (wen ). when wen is asserted, data is written into the fifo on the rising edge of the wclk signal. while wen is held active, data is continually written in to the fifo on each cycle. the output port is controlled in a si milar manner by a free-running read clock (rclk) and a read enable pin (ren ). in addition, the cy7c42x5 have an output enable pin (oe ). the read and write clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. clock frequencies up to 100 mhz are achievable. retransmit and synchronous al most full/almost empty flag features are available on these devices. depth expansion is possible using the cascade input (wxi , rxi ), cascade output (wxo , rxo ), and first load (fl ) pins. the wxo and rxo pins are connected to the wxi and rxi pins of the next device, and the wxo and rxo pins of the last device should be connected to the wxi and rxi pins of the first device. the fl pin of the first device is tied to vss and the fl pin of all the remaining devices should be tied to vcc. the cy7c42x5 provides five status pins. these pins are decoded to determine one of five states: empty, almost empty, half full, almost full, and full (see table 2). the half full flag shares the wxo pin. this flag is valid in the standalone and width-expansion configurations. in the depth expansion, this pin provides the expansion out (wxo ) information that is used to signal the next fifo when it will be activated. the empty and full flags are synchronous, i.e., they change state relative to either the read clock (rclk) or the write clock (wclk). when entering or exiting the empty states, the flag is updated exclusively by the rclk. the flag denoting full states is updated exclusively by wclk. the synchronous flag archi- tecture guarantees that the flags will remain valid from one clock cycle to the next. as mentio ned previously, the almost empty/almost full flags become synchronous if the vcc/smode is tied to vss. all conf igurations are fabricated using an advanced 0.65m n-well cmos technology. input esd protection is greater than 2001v , and latch-up is prevented by the use of guard rings. [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 2 of 25 logic block diagram tri?state output register read control flag logic write control write pointer read pointer reset logic expansion logic input register flag program register ren rclk ff ef pae q 0?17 wen wclk rs fl /rt wxi oe ram array 64 x 18 256 x 18 512 x 18 1k x 18 2k x 18 4k x 18 paf wxo /hf rxi rxo smode d 0?17 [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 3 of 25 contents pin configuration ............................................................. 4 pin definitions .................................................................. 5 selection guide ................................................................ 5 architecture ...................................................................... 6 resetting the fifo ............................................................ 6 fifo operation ................................................................. 6 programming .................................................................... 6 flag operation .................................................................. 7 full flag ....................................................................... 7 empty flag .................................................................. 7 programmable almost empty/ almost full flag ........... 7 retransmit ......................................................................... 7 width expansion configuration ...................................... 8 depth expansion configuration ...................................... 8 maximum ratings ........................................................... 10 operating range ............................................................. 10 electrical characteristics ............................................... 10 capacitance ..................................................................... 10 switching characteristics .............................................. 11 switching waveforms .................................................... 12 ordering information ...................................................... 21 256 x 18 synchronous fifo ..................................... 21 512 x 18 synchronous fifo ..................................... 21 1k x 18 synchronous fifo ... .............. .............. ........ 21 4k x 18 synchronous fifo ... .............. .............. ........ 21 ordering code definitions ..... .................................... 21 package diagrams .......................................................... 22 acronyms ........................................................................ 23 document conventions ................................................. 23 units of measure ....................................................... 23 sales, solutions, and legal information ...................... 25 worldwide sales and design s upport ......... .............. 25 products .................................................................... 25 psoc solutions ......................................................... 25 [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 4 of 25 pin configuration figure 1. tqfp (top view) [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 5 of 25 selection guide description -10 -15 maximum frequency (mhz) 100 66.7 maximum access time (ns) 8 10 minimum cycle time (ns) 10 15 minimum data or enable set-up (ns) 3 4 minimum data or enable hold (ns) 0.5 1 maximum flag delay (ns) 8 10 operating current (i cc2 ) (ma) @ 20mhz commercial 45 45 industrial 50 50 parameter cy7c4205 cy7c4215 cy7c4225 cy7c4245 density 256 x 18 512 x 18 1k x 18 4k x 18 packages 64-pin tqfp (14 x 14, 10 x 10) 64-pin tqfp (14 x 14, 10 x 10) 64-pin tqfp (14 x 14, 10 x 10) 64-pin tqfp (14 x 14, 10 x 10) pin definitions signal name description io function d 0 ? 17 data inputs i data inputs for an 18-bit bus. q 0 ? 17 data outputs o data outputs for an 18-bit bus. wen write enable i enables the wclk input. ren read enable i enables the rclk input. wclk write clock i the rising edge clocks data into the fifo when wen is low and the fifo is not full. when ld is asserted, wclk writes data into the programmable flag-offset register. rclk read clock i the rising edge clocks data out of the fifo when ren is low and the fifo is not empty. when ld is asserted, rclk reads data out of the programmable flag-offset register. wxo /hf write expansion out/half full flag o dual-mode pin. single device or width expans ion - half full status flag. cascaded ? write expansion out signal, connected to wxi of next device. ef empty flag o when ef is low, the fifo is empty. ef is synchronized to rclk. ff full flag o when ff is low, the fifo is full. ff is synchronized to wclk. pae programmable almost empty o when pae is low, the fifo is almost empty based on the almost empty offset value programmed into the fifo. pae is asynchronous when v cc /smode is tied to v cc ; it is synchronized to rclk when v cc /smode is tied to v ss . paf programmable almost full o when paf is low, the fifo is almost full based on the almost full offset value programmed into the fifo. paf is asynchronous when v cc /smode is tied to v cc ; it is synchronized to wclk when v cc /smode is tied to v ss . ld load i when ld is low, d 0 ? 17 (o 0 ? 17 ) are written (read) into (from) the program- mable-flag-offset register. fl /rt first load/ retransmit i dual-mode pin. cascaded ? the first device in the daisy chain will have fl tied to v ss ; all other devices will have fl tied to v cc . in standard mode of width expansion, fl is tied to v ss on all devices. not cascaded ? tied to v ss . retransmit function is also available in standalone mode by strobing rt. wxi write expansion input i cascaded ? connected to wxo of previous device. not cascaded ? tied to v ss . rxi read expansion input i cascaded ? connected to rxo of previous device. not cascaded ? tied to v ss . [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 6 of 25 architecture the cy7c42x5 consists of an array of 256 to 1 k words & 4 k words of 18 bits each (implemented by a dual-port array of sram cells), a read pointer, a write pointer, control signals (rclk, wclk, ren , wen , rs ), and flags (ef , pae , hf , paf , ff ). the cy7c42x5 also includes the control signals wxi , rxi , wxo , rxo for depth expansion. resetting the fifo upon power-up, the fifo must be reset with a reset (rs ) cycle. this causes the fifo to enter the empty condition signified by ef being low. all data outputs go low after the falling edge of rs only if oe is asserted. in order for the fifo to reset to its default state, a falling edge must occur on rs and the user must not read or write while rs is low. fifo operation when the wen signal is active (low), data present on the d 0-17 pins is written into the fifo on each rising edge of the wclk signal. similarly, when the ren signal is active low, data in the fifo memory will be presented on the q 0 ? 17 outputs. new data will be presented on each rising edge of rclk while ren is active low and oe is low. ren must set up t ens before rclk for it to be a valid read function. wen must occur t ens before wclk for it to be a valid write function. an output enable (oe ) pin is provided to three-state the q 0?17 outputs when oe is deasserted. when oe is enabled (low), data in the output register will be available to the q 0 ? 17 outputs after t oe . if devices are cascaded, the oe function will only output data on the fifo that is read enabled. the fifo contains overflow circuitry to disallow additional writes when the fifo is full, and underflow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its q 0 ? 17 outputs even after additional reads occur. programming the cy7c42x5 devices contain two 12-bit offset registers. data present on d 0?11 during a program write will determine the distance from empty (full) that the almost empty (almost full) flags become active. if the user elects not to program the fifo?s flags, the default offset values are used (see table 2 ). when the load ld pin is set low and wen is set low, data on the inputs d 0?11 is written into the empty of fset register on the first low-to-high transition of the write clock (wclk). when the ld pin and wen are held low then data is written into the full offset register on the second low-to-high transition of the write clock (wclk). the third transition of the write clock (wclk) again writes to the empt y offset register (see table 1 ). writing all offset registers does not have to occur at one time. one or two offset registers can be writte n and then, by bringing the ld pin high, the fifo is returned to normal read/write operation. when the ld pin is set low, and wen is low, the next offset register in sequence is written. the contents of the offset regi sters can be read on the output lines when the ld pin is set low and ren is set low; then, data can be read on the low-to -high transition of the read clock (rclk). note 1. the same selection sequence applies to reading from the registers. ren is enabled and read is performed on the low-to-high transition of rclk. rxo read expansion output o cascaded ? connected to rxi of next device. rs reset i resets device to empty c ondition. a reset is required bef ore an initial read or write operation after power-up. oe output enable i when oe is low, the fifo?s data outputs drive the bus to wh ich they are connected. if oe is high, the fifo?s outputs are in high z (high-impedance) state. v cc /smode synchronous almost empty/ almost full flags i dual-mode pin. asynchronous almost empty/almost full flags ? tied to v cc . synchronous almost empty/almost full flags ? tied to v ss . (almost empty synchro- nized to rclk, almost full synchronized to wclk.) pin definitions (continued) signal name description io function table 1. write offset register ld wen wclk [1] selection 0 0 writing to offset registers: empty offset full offset 0 1 no operation 1 0 write into fifo 1 1 no operation [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 7 of 25 flag operation the cy7c42x5 devices provide five flag pins to indicate the condition of the fifo contents . empty and full are synchronous. pae and paf are synchronous if v cc /smode is tied to v ss . full flag the full flag (ff ) will go low when device is full. write operations are inhibited whenever ff is low regardless of the state of wen . ff is synchronized to wclk, i.e., it is exclusively updated by each rising edge of wclk. empty flag the empty flag (ef ) will go low when the device is empty. read operations are inhibited whenever ef is low, regardless of the state of ren . ef is synchronized to rclk, i.e., it is exclusively updated by each rising edge of rclk. programmable almost empty/almost full flag the cy7c42x5 features programmable almost empty and almost full flags. each flag can be programmed (described in the programming section) a sp ecific distance from the corresponding boundary flags (empty or full). when the fifo contains the number of words or fewer for which the flags have been programmed, the paf or pae will be asserted, signifying that the fifo is either almost full or almost empty. see table 2 for a description of programmable flags. when the smode pin is tied low, the paf flag signal transition is caused by the rising edge of the write clock and the pae flag transition is caused by the rising edge of the read clock. retransmit the retransmit feature is beneficial when transferring packets of data. it enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. the retransmit (rt) input is ac tive in the standalone and width expansion modes. the retransmit feature is intended for use when a number of writes equal to or less than the depth of the fifo have occurred since the last rs cycle. a high pulse on rt resets the internal read pointer to the first physical location of the fifo. wclk and rclk may be free running but must be disabled during and trtr after the retransmit pulse. with every valid read cycle after retransmit, previously accessed data is read and the read pointer is increm ented until it is equal to the write pointer. flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. data written to the fifo after activation of rt are transmitted also. the full depth of the fifo can be repeatedly retransmitted. table 2. flag truth table number of words in fifo ff paf hf pae ef cy7c4205 - 256 x 18 cy7c4215 - 512 x 18 00 hhhll 1 to n [2] 1 to n [2] hh h l h (n + 1) to 128 (n + 1) to 256 h h h h h 129 to (256 ?? (m + 1)) 257 to (512 ?? (m + 1)) h h l h h (256 ?? m) [] to 255 (512 ?? m) [] to 511 h l l h h 256 512 l l l h h number of words in fifo ff paf hf pae ef cy7c4225 - 1k x 18 cy7c4245 - 4k x 18 00 hhhll 1 to n [2] 1 to n [2] hh h l h (n + 1) to 512 (n + 1) to 2048 h h h h h 513 to (1024 ?? (m + 1)) 2049 to (4096 ?? (m + 1)) h h l h h (1024 ?? m) [3] to 1023 (4096 ?? m) [3] to 4095 h l l h h 1024 4096 l l l h h notes 2. n = empty offset (default values: cy7c4205 n = 31, cy7c4215 n = 63, cy7c4225/cy7c4245 n = 127). 3. m = full offset (default values: cy7c4205 n = 31, cy7c4215 n = 63, cy7c4225/cy7c4245 n = 127). [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 8 of 25 width expansion configuration the cy7c42x5 can be expanded in width to provide word widths greater than 18 in increments of 18. during width expansion mode all control line inputs are common and all flags are available. empty (full) flags should be created by anding the empty (full) flags of every fifo. this technique will avoid ready data from the fifo that is ?staggered? by one clock cycle due to the variations in skew between rclk and wclk. figure 2 demonstrates a 36-word width by using two cy7c42x5. depth expansion configuration (with program- mable flags) the cy7c42x5 can easily be adapted to applications requiring more than 256/512/1024/4096 words of buffering. figure 3 shows depth expansion using three cy7c42x5s. maximum depth is limited only by signal loading. follow these steps: 1. the first device must be designated by grounding the first load (fl ) control input. 2. all other device s must have fl in the high state. 3. the write expansion out (wxo ) pin of each device must be tied to the write expansion in (wxi ) pin of the next device. 4. the read expansion out (rxo ) pin of each device must be tied to the read expansion in (rxi ) pin of the next device. 5. all load (ld ) pins are tied together. 6. the half-full flag (hf ) is not available in the depth expansion configuration. 7. ef , ff , pae , and paf are created with composite flags by oring together these respective flags for monitoring. the composite pae and paf flags are not precise. figure 2. block diagram of synchronous fifo memories used in a width expansion configuration ff ff ef ef write clock (wclk) write enable (wen ) load (ld ) programmable(pae ) half full flag (hf ) full flag (ff ) 7c4205 7c4215 7c4225 7c4245 7c4205 7c4215 7c4225 7c4245 18 36 datain (d) reset (rs ) 18 reset (rs ) read clock (rclk) read enable (ren ) output enable(oe ) programmable(paf ) emptyflag (ef ) 18 dataout (q) 18 36 first load (fl ) write expansion in (wxi ) read expansion in (rxi ) first load (fl ) write expansion in (wxi ) read expansion in (rxi ) [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 9 of 25 figure 3. block diagram of synchronous fifo memory with programmable flags used in depth expansion configuration 42x5?23 writeclock (wclk) write enable (wen ) reset (rs ) load (ld ) ff paf paf ff ef pae pae ef wxi rxi firstload (fl ) read clock (rclk) read enable (ren ) output enable (oe ) wxo rxo 7c4205 7c4215 7c4225 7c4245 paf ff ef pae wxi rxi wxo rxo 7c4205 7c4215 7c4225 7c4245 v cc firstload (fl ) paf ff ef pae wxi rxi wxo rxo 7c4205 7c4215 7c4225 7c4245 v cc firstload (fl ) datain (d) dataout (q) [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 10 of 25 maximum ratings [6] (exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested) storage temperature ?????????????????????????????????? ? 65 ? c to +150 ? c ambient temperature with power applied ??????????????????????????????????????????????? ? 55 ? c to +125 ? c supply voltage to ground potential ???????????????? ? 0.5 v to +7.0 v dc voltage applied to outputs in high-z state ??????????????????????????????????????????????????? ? 0.5 v to +7.0 v dc input voltage ????????????????????????????????????????????????? 3.0 v to +7.0 v output current into outputs (low) .............................. 20 ma static discharge voltage ........................................... >2001 v (per mil-std-883, method 3015) latch-up current ...................................................... >200 ma operating range range ambient temperature v cc commercial 0 ? c to +70 ?? c 5 v 10% industrial [4] -40 ?? c to +85 ?? c 5 v 10% electrical characteristics over the operating range [6] parameter description test conditions -10 -15 unit min max min max v oh output high voltage v cc = min i oh = ? 2.0 ma 2.4 ? 2.4 ? v v ol output low voltage v cc = min i ol = 8.0 ma ? 0.4 ? 0.4 v v ih [7] input high voltage 2.2 v cc 2.2 v cc v v il [7] input low voltage ? 3.0 0.8 ? 3.0 0.8 v i ix input leakage current v cc = max ? 10 +10 ? 10 +10 ? a i os [8] output short circuit current v cc = max v out = gnd ? 90 ? ? 90 ? ? a i ozl i ozh output off, high z current oe > v ih , v ss < v o < v cc ? 10 +10 ? 10 +10 ? a i cc [9] operating current v cc = max i out = 0 ma com?l ? 45 ? 45 ma ind?l ? 50 ? 50 ma i sb [10] standby current v cc = max i out = 0 ma com?l ? 10 ? 10 ma ind?l ? 15 ? 15 ma capacitance [11] parameter description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 5.0 v 5pf c out output capacitance 7 pf notes 4. t a is the ?instant on? case temperature. 5. see the last page of this specification for group a subgroup testing information. 6. the voltage on any input or i/o pin cannot exceed the power pin during power-up 7. the v ih and v il specifications apply for all inputs except wxi , rxi . the wxi , rxi pin is not a ttl input. it is connected to either rxo , wxo of the previous device or v ss . 8. test no more than one output at a time for not more than one second. 9. input signals switch from 0 v to 3 v with a rise/fall time less than 3 ns, clocks and clock enables switch at 20 mhz, while t he data inputs switch at 10 mhz. outputs are unloaded. 10. all input signals are connected to v cc . all outputs are unloaded. 11. tested initially and after any design or process changes that may affect these parameters. [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 11 of 25 figure 4. ac test loads and waveforms [12, 13] switching characteristics over the operating range parameter description -10 -15 unit min max min max t s clock cycle frequency ? 100 ? 66.7 mhz t a data access time 2 8 2 10 ns t clk clock cycle time 10 ? 15 ? ns t clkh clock high time 4.5 ? 6 ? ns t clkl clock low time. 4.5 ? 6 ? ns t ds data set-up time 3 ? 4 ? ns t dh data hold time 0.5 ? 1 ? ns t ens enable set-up time 3 ? 4 ? ns t enh enable hold time 0.5 ? 1 ? ns t rs reset pulse width [14] 10 ? 15 ? ns t rsr reset recovery time 8 ? 10 ? ns t rsf reset to flag and output time ? 10 ? 15 ns t prt retransmit pulse width 12 ? 15 ? ns t rtr retransmit recovery time 12 ? 15 ? ns t olz output enable to output in low z [15] 0 ? 0 ? ns t oe output enable to output valid 3 7 3 8 ns t ohz output enable to output in high z [15] 3 7 3 8 ns t wff write clock to full flag ? 8 ? 10 ns t ref read clock to empty flag ? 8 ? 10 ns t pafasynch clock to programmable almost-full flag [16] (asynchronous mode, v cc /smode tied to v cc ) ? 12 ? 16 ns t pafsynch clock to programmable almost-full flag (synchronous mode, v cc /smode tied to v ss ) ? 8 ? 10 ns t paeasynch clock to programmable almost-empty flag [16] (asynchronous mode, v cc /smode tied to v cc ) ? 12 ? 16 ns t paesynch clock to programmable almost-full flag (synchronous mode, v cc /smode tied to v ss ) ? 8 ? 10 ns notes 12. c l = 30 pf for all ac parameters except for t ohz . 13. c l = 5 pf for t ohz . 14. pulse widths less than minimum values are not allowed. 15. values guaranteed by design, not currently tested. 16. t pafasynch , t paeasynch , after program register write will not be valid until 5 ns + t paf(e) . 3.0 v 5v output r1 = 1.1 k ? r2 =680 ? c l including jig and scope gnd 90% 10% 90% 10% ?? 3 ns output vth = 1.91 v equivalent to: thvenin equivalent rth = 410 ? all input pulses ?? 3 ns [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 12 of 25 t hf clock to half-full flag ? 12 ? 16 ns t xo clock to expansion out ? 7 ? 10 ns t xi expansion in pulse width 3 ? 6.5 ? ns t xis expansion in set-up time 4.5 ? 5 ? ns t skew1 skew time between read clock and write clock for full flag 5 ? 6 ? ns t skew2 skew time between read clock and write clock for empty flag 5 ? 6 ? ns t skew3 skew time between read clock and write clock for programmable almost empty and programmable almost full flags. 10 ? 15 ? ns switching waveforms figure 5. write cycle timing note 17. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current cl ock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk edge. switching characteristics over the operatin g range (continued) parameter description -10 -15 unit min max min max t clkh t clkl no operation t ds t skew1 t ens wen t clk t dh t wff t wff t enh wclk ?d 17 ff ren rclk [17] [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 13 of 25 figure 6. read cycle timing figure 7. reset timing [19] notes 18. t skew2 is the minimum time between a rising wclk edge and a rising rclk edge to guarantee that ef will go high during the current clock cycle. it the time between the rising edge of wclk and the rising edge of rclk is less than t skew2 , then ef may not change state until the next rclk edge. 19. the clocks (rclk, wclk) can be free-running during reset. 20. after reset, the outputs will be low if oe = 0 and three-state if oe = 1. switching waveforms (continued) t clkh t clkl no operation t skew2 wen t clk t ohz t ref t ref rclk q 0 ?q 17 ef ren wclk oe t oe t ens t olz t a t enh valid data [18] t rs t rsr q 0 ?q 17 rs t rsf t rsf t rsf oe = 1 oe = 0 ren ,wen , ld ef ,pae ff ,paf , hf [20] [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 14 of 25 figure 8. first data word latency after reset with simultaneous read and write figure 9. empty flag timing notes 21. when t skew2 > minimum specification, t frl (maximum) = t clk + t skew2 . when t skew2 < minimum specification, t frl (maximum) = either 2*t clk + t skew2 or t clk + t skew2 . the latency timing applies only at the empty boundary (ef = low). 22. the first word is available the cycle after ef goes high, always. switching waveforms (continued) d 0 (firstvalid write) t skew2 wen wclk ef ren oe t oe t ens t olz t ds rclk t ref t a t frl d 1 d 2 d 3 d 4 d 0 d 1 d 0 ?d 17 t a [22] [21] q 0 ?q 17 d1 d0 t ens t skew2 wen wclk ef ren oe t ds t enh rclk t ref t a t frl d 0 ?d 17 d0 t skew2 t frl t ref t ds t ens t enh t ref [21] [21] q 0 ?q 17 [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 15 of 25 figure 10. full flag timing figure 11. half-full flag timing note 23. t skew1 is the minimum time between a rising rclk edge and a rising wclk edge to guarantee that ff will go high during the current clock cycle. if the time between the rising edge of rclk and the rising edge of wclk is less than t skew1 , then ff may not change state until the next wclk edge. switching waveforms (continued) next data read data write no write data in output register ff wclk ren oe rclk t a d 0 ?d 17 dataread t skew1 t ds t ens t enh wen t wff t a t skew1 t ens t enh t wff data write no write t wff low [17] [17] q 0 ?q 17 t enh wclk hf ren rclk t clkh t hf t ens half full+1 or more t clkl t ens half full or less half full or less t hf wen [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 16 of 25 figure 12. programmable almost empty flag timing figure 13. programmable almost empty flag timing (applies only in smode (smode is low) notes: 24. pae offset ?? n. number of data words into fifo already = n. 25. pae offset ?? n. 26. t skew3 is the minimum time between a rising wclk and a rising rclk edge for pae to change state during that clock cycle. if the time between the edge of wclk and the rising rclk is less than t skew3 , then pae may not change state until the next rclk. 27. if a read is performed on this rising edge of the read clock, there will be empty + (n ? 1) words in the fifo when pae goes low. switching waveforms (continued) t enh wclk pae ren rclk t clkh t pae t ens n+1 ? words in fifo t clkl t ens t pae n words in fifo [24] wen t enh wclk pae rclk t clkh t ens t clkl t ens t paesynch n + 1 words infifo t enh t ens t paesynch ren wen t skew3 [26] note 27 note 25 [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 17 of 25 figure 14. programmable almost full flag timing figure 15. programmable almost full flag timing (applies only in smode (smode in low)) notes: 28. paf offset = m. number of data words written into fifo already = 64 ? m + 1 for the cy7c4205, 256 ? m + 1 for the cy7c4205, 512 ??? m + 1 for the cy7c4215. 1024 ? m + 1 for the cy7c4225, 2048 ? m + 1 for the cy7c4235, and 4096 ? m + 1 for the cy7c4245. 29. paf is offset = m. 30. 64 ? m words in cy7c4205, 256 ? m words in cy7c4205, 512 ?? m words in cy7c4215. 1024 ? m words in cy7c4225, 2048 ? m words in cy7c4235, and 4096 ? m words in cy7c4245. 31. 64 ?? m + 1 words in cy7c4205, 256 ?? m + 1 words in cy7c4205, 512 ? m + 1 words in cy7c4215, 1024 ? m + 1 cy7c4225, 2048 ? m + 1 in cy7c4235, and 4096 ? ? m + 1 words in cy7c4245. 32. if a write is performed on this rising edge of the write clock, there will be full ? (m?1) words of the fifo when paf goes low. 33. paf offset = m. 34. t skew3 is the minimum time between a rising rclk and a rising wclk edge for paf to change state during that clock cycle. if the time between the edge of rclk and the rising edge of wclk is less than t skew3 , then paf may not change state until the next wclk rising edge. switching waveforms (continued) t enh wen wclk ren rclk t clkh t paf t ens t clkl t ens t paf full ? m words in fifo full ? m + 1 words in fifo [31] paf [29] note 28 [30] t enh wclk paf rclk t clkh t ens full ? m words in fifo t clkl t ens full ? m + 1 words in fifo t enh t ens t paf ren t skew3 t pafsynch [34] note 32 wen [30] note 33 [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 18 of 25 figure 16. write programmable registers figure 17. read programmable registers figure 18. write expansion out timing note: 35. write to last physical location. switching waveforms (continued) t enh ld wclk t clkh t ens t clkl pae offset d 0 ?d 17 wen t ens paf offset pae offset t clk t ds t dh d 0 ?d 11 t enh ld rclk t clkh t ens t clkl pae offset ren t ens paf offset pae offset t clk unknown t a q 0 ?q 17 wen wclk wxo t clkh t ens t xo t xo note 35 [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 19 of 25 figure 19. read expansion out timing figure 20. write expansion in timing figure 21. read expansion in timing figure 22. retransmit timing [37, 38, 39] notes: 36. read from last physical location. 37. clocks are free running in this case. 38. the flags may change state during retransmit as a result of t he offset of the read and write pointers, but flags will be val id at t rtr . 39. for the synchronous pae and paf flags (smode), an appropriate clock cycle is necessary after t rtr to update these flags. switching waveforms (continued) ren rclk rxo t clkh t ens t xo t xo note 36 wclk wxi t xi t xis rclk rxi t xi t xis ren /wen fl /rt t prt t rtr ef /ff and/all async flags hf /pae /paf [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 20 of 25 figure 23. typical ac and dc characteristics supply voltage (v) normalized t a vs.supply voltage normalized supply current vs. supply voltage normalized t a vs. ambient temperature normalized supply current vs. ambient temperature frequency (mhz) normalized supply current vs. frequency supply voltage (v) v cc =5.0v normalized i cc normalized i cc ambient temperature ( c) v in =3.0v t a =25 c f=100 mhz v in =3.0v v cc =5.0v f=100 mhz normalized i cc v cc =5.0v t a =25 c v in =3.0v capacitance (pf) normalized t a typical t a change vs. output loading v cc =5.0v t a =25 c output sourcecurrent vs. output voltage output voltage (v) output sink current vs. output voltage output voltage (v) outputs ource current (ma) output sink curent (ma) normalized t a ambient temperature normalized t a 4 4.5 5 5.5 6 0.6 0.8 1.0 1.2 1.4 ? 55 25 125 0.8 0.9 1.0 1.1 1.2 0255075100 0.6 0.7 0.8 0.9 1.0 1.1 0.8 0.9 1.0 1.1 1.2 4 4.5 5 5.5 6 ? 55 25 125 0.5 .75 1.0 1.25 1.50 t a =25 c .50 275 550 825 1000 ? 5.0 10 25 40 25 35 45 55 012 345 0123 4 0 20 40 60 80 100 120 140 120 t a =25 c v cc =5.0v t a =25 c v cc =5.0v ( c) f
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 21 of 25 ordering information ordering code definitions 256 x 18 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4205-10axc 51-85046 64-pin (14 x 14) thin quad flatpack (pb-free) commercial 512 x 18 synchronous fifo speed (ns) ordering code package name package type operating range 15 cy7c4215-15axi 51-85046 64-pin (14 x 14) thin quad flatpack (pb-free) industrial 1k x 18 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4225-10axi 51-85046 64-pin (14 x 14) thin quad flatpack (pb-free) industrial 15 cy7c4225-15axc 51-85046 64-pin (14 x 14) thin quad flatpack (pb-free) commercial CY7C4225-15ASXC 51-85051 64-pin (10 x 10) thin quad flatpack (pb-free) 4k x 18 synchronous fifo speed (ns) ordering code package name package type operating range 10 cy7c4245-10axi 51-85046 64-pin (14 x 14) thin quad flatpack (pb-free) industrial 15 cy7c4245-15axc 51-85046 64-pin (14 x 14) thin quad flatpack (pb-free) commercial cy7c4245-15asxc 51-85051 64-pin (10 x 10) thin quad flatpack (pb-free) cy family: dual-port sram 7 c 4 technology: cmos company id: cy = cypress fifo 5 x18 temperature grade: c = commercial, i = industrial xx x x c, i pb-free (rohs compliant) package: a = tqfp, as = stqfp speed grade: 10 ns or 15 ns 2x depth: 20 = 256; 21 = 512 22 = 1 k; 24 = 4 k [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 22 of 25 package diagrams figure 24. 64-pin thin plastic quad flat pack (14 x 14 x 1.4 mm), 51-85046 51-85046 *e [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 23 of 25 acronyms document conventions units of measure figure 25. 64-pin thin plastic quad flat pack (10 x 10 x 1.4 mm), 51-85051 package diagrams (continued) 51-85051 *b acronym description cmos complementary metal oxide semiconductor fifo first-in first-out oe output enable tqfp thin quad flat package ttl transistor-transistor logic symbol unit of measure ns nano seconds vvolts a micro amperes ma milli amperes mv milli volts mw milli watts mhz mega hertz pf pico farad c degree celcius wwatts [+] feedback
cy7c4205/cy7c4215 cy7c4225/cy7c4245 document number: 001-45652 rev. *b page 24 of 25 document history page document title: cy7c4205/cy7c4215/cy7c4225/cy7c4245, 256/512/1k/4k x 18 synchronous fifos document number: 001-45652 rev. ecn no. issue date orig. of change description of change ** 2489087 see ecn vkn this document is recreated from t he existing pdf file on web. this is provided a new spec number. *a 3094407 11/24/10 admu removed following invalid parts from the ordering information table. cy7c4205-15ac cy7c4205-15axc cy7c4215-15ai cy7c4225-10ai cy7c4225-15asc cy7c4235-15axc cy7c4245-10ai cy7c4245-10axc cy7c4245-10asxc cy7c4245-15jxc added ordering code definitions. updated package diagrams to latest revision. *b 3264857 05/25/2011 admu removed obsolete part information. removed 51-85005 package diagram. updated package diagrams 51-85046. title modified, ordering code definition updated. added acronyms and units of measure table removed plcc figure from pin confirguration and the references. [+] feedback
document number: 001-45652 rev. *b revised may 25, 2011 page 25 of 25 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c4205/cy7c4215 cy7c4225/cy7c4245 ? cypress semiconductor corporation, 2010-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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